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a65h73361/a65h83181 series 128k x 36 & 256k x 18 late write synchronous preliminary fast sram with pipelined data output preliminary ( february , 1999, version 2.0) amic technology, inc. document title 128k x 36 & 256k x 18 late write synchronous fast sram with pipelined data output revision history rev. no. history issue date remark 2.0 add jtag standard february 12, 1999 preliminary
a65h73361/a65h83181 series 128k x 36 & 256k x 18 late write synchronous preliminary fast sram with pipelined data output preliminary ( february , 1999, version 2.0) 1 amic technology, inc. features n fast access times: 2.5/3.0/3.5ns n 128k x 36 or 256 k x 18 organizations n cmos technology n register to register synchronous operation with self- timed late write n single +3.3v 5% power supply n individual byte write and global write n hstl input & output levels n boundary scan(jtag) ieee 1149.1 compatible n asynchronous output enable n sleep mode (zz) n programmable impedance output drivers n jedec standard pinout and boundary scan order n 7 x 17 bump plastic ball grid array (pbga) package general description the a65h73361 and a65h83181 are 128k words by 36 bits and 256k words by 18 bits late write synchronous 4mb srams built using high performance cmos process. the differential clock are used to control the timing of read/write operation and all internal operations are self- timed. the positive edge triggered ck clock input controls all addresses write-enables and synchronous select and data ins are registered. the data outs are controlled by the output registers off the next positive clock edge to be updated. the internal write buffer enables write data to be accepted on the rising edge of the clock one cycle after address and control signals. the sram uses hstl i/o interfaces with programmable impedance output drivers allowing the outputs to match the impedance of the circuit traces which reduces signal reflections.
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 2 amic technology, inc. pin configuration a65h73361 v ddq sa 7 nc sa 16 sa 14 v ddq 1 2 3 4 5 6 7 nc nc sa 8 nc sa 11 nc nc nc sa 6 sa 9 v dd sa 10 sa 15 nc dq 18 dq 27 v ss nc m 1 v dd nc nc zz v ddq tms tdi tck tdo nc a b c d e f g h j k l m n p r t u v ddq nc nc m 2 v ss sa 5 dq 19 sa 4 sa 12 sa 3 sa 2 sa 13 sa 1 dq 1 dq 0 dq 3 dq 2 v ddq sw v ss dq 4 v ddq dq 32 dq 33 sbw d ck sbw a dq 6 dq 5 dq 34 dq 35 v ss ck v ss dq 8 dq 7 v ddq v dd v ref v dd v ref v dd v ddq dq 25 dq 26 nc v ss dq 17 dq 16 dq 23 dq 24 sbw c nc sbw b dq 15 dq 14 v ddq dq 22 v ss g v ss dq 13 v ddq dq 20 dq 21 v ss ss v ss dq 12 dq 11 v ss zq v ss dq 10 dq 9 dq 31 dq 30 dq 25 v ss dq 29 v ss v ss sa 0 a65h83181 v ddq sa 7 nc sa 16 sa 14 v ddq 1 2 3 4 5 6 7 nc nc sa 8 nc sa 11 nc nc nc sa 6 sa 9 v dd sa 10 sa 15 nc dq 9 nc v ss nc m 1 v dd nc zz v ddq tms tdi tck tdo nc a b c d e f g h j k l m n p r t u v ddq nc m 2 v ss sa 5 nc sa 4 sa 13 sa 3 nc sa 17 sa 1 nc dq 0 dq 3 nc v ddq sw v ss nc v ddq dq 14 nc ck sbw a dq 6 nc nc dq 17 v ss ck v ss nc dq 7 v ddq v dd v ref v dd v ref v dd v ddq dq 16 nc nc v ss dq 8 nc nc dq 15 sbw b nc nc dq 5 v ddq nc v ss g v ss dq 4 v ddq nc dq 12 v ss ss v ss nc dq 2 v ss zq v ss dq 1 nc dq 13 nc dq 10 v ss dq 11 v ss v ss sa 0 v ss v ss v ss sa 2 sa 12 v ss
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 3 amic technology, inc. block diagram 128kx36 or 256kx18 array dq0 - dq35 column decoder read/write amp row decoder write buffer 2:1 mux 2:1 mux match wr add register data out registor rd add register sw register sbw register sw register sbw register sa0-sa17 ck latch ss zz sw sbw latch ss register ss register g pin description sa0-sa17 address input (x18 : sa0 - sa17, x36 : sa0 - sa16) g asynchronous output enable dq0-dq35 data i/o (x18 : dq0 - dq17, x36 : dq0 - dq35) ss synchronous select ck , ck differential input register clocks m1, m2 for boundary scan purpose sw write enable. global v rep (2) hstl input reference voltage sbwa write enable. byte a (dq0-dq8) v dd power supply (+3.3v) sbwb write enable. byte b (dq9-dq17) v ss ground sbwc write enable. byte c (dq18-dq26) v ddq output power supply sbwd write enable. byte d (dq27-dq35) zz asynchronous sleep mode tms, tdi, tck ieee 1149.1 test inputs(lvttl levels) zq output driver impedance control tdo ieee 1149.1 test output(lvttl level) nc no connect
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 4 amic technology, inc. clock truth table k zz ss sw sbwa sbwb sbwc sbwd dq(n) dq(n+1) mode l ? h l l h x x x x x d out 0-35 read cycle all bytes l ? h l l l l h h h x d in 0-8 write cycle 1st byte l ? h l l l h l h h x d in 9-17 write cycle 2nd byte l ? h l l l h h l h x d in 18-26 write cycle 3rd byte l ? h l l l h h h l x d in 27-35 write cycle 4th byte l ? h l l l l l l l x d in 0-35 write cycle all byte l ? h l l l h h h h x high-z abort write cycle l ? h l h x x x x x x high-z deselect cycle x h x x x x x x high-z high-z sleep mode clock truth table operation g dq read l d out 0-35 read h high-z sleep(zz=h) x high-z write( sw =l) x d in deselect( ss =h) x high-z
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 5 amic technology, inc. absolute maximum ratings* power supply voltage(v dd ) . . . . . . . . . . -0.5v to +4.6v voltage relative to gnd for any pin except v dd (v in , v out ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5v power dissipation (p d ) . . . . . . . . .. . . . . . . . . . .. . .1.0w operating temperature (topr). . . . . . . . .. . 0 c to 70 c storage temperature (tbias) . . . . . . .. .. . -10 c to 85 c storage temperature(tstg). . . . . . . . . . .-55 c to 125 c *comments stresses above those listed under "absolute maximum ratings" may cause permanent damage to this device. these are stress ratings only. functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied and exposure the absolute maximum rating conditions for extended periods may affect device reliability. recommended dc operating conditions (t j = 0 to 110 c ) parameter symbol min. typ. max. units notes supply voltage v dd 3.15 3.3 3.47 v 1 output driver supply voltage v ddq 1.4 1.5 1.6 v 1 input high voltage v ih v ref +0.1 - v ddq +0.3 v 1, 2 input low voltage v il -0.3 - v ref -0.1 v 1, 3 input reference voltage v ref 0.68 0.75 0.90 v 1, 6 clocks signal voltage v in-clk -0.3 - v ddq +0.3 v 1, 4 differential clocks signal voltage v dif-clk 0.1 - v ddq +0.6 v 1, 5 clocks common mode voltage v cm-clk 0.55 - 0.90 v 1 output current i out - 5 8 ma 1.all voltage reference to v ss. all v dd v ddq and v ss pins must be connected. 2.v ih (max)dc = v dd + 0.3v, v ih (max)ac = v dd + 1.5v (pulse width 4.0ns). 3.v il (min)dc = -0.3v, v il (min)ac = -1.5 v (pulse width 4.0ns). 4.v in-clk specifies the maximum allowable dc excursions of each differential clock ( ck , ck ). 5.v dif-clk specifies the minimum clock differential voltage required for switching. 6.peak to peak ac component superimposed on v ref may not exceed 5% of v ref .
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 6 amic technology, inc. dc electrical characteristics (t j = 0 to +110 c, v dd = 3.3v 5% ) parameter symbol min. max. units notes average power supply operating current-x36 (i out = 0, v in = v ih or v il , zz & ss = v il ) l dd5 l dd6 l dd7 - - tbd ma 1 average power supply operating current-x18 (i out = 0, v in = v ih or v il , zz & ss = v il ) l dd5 l dd6 l dd7 - - tbd ma 1 power supply standby current (zz = v ih , all other inputs = v ih or v il , i out =0) ( ss = v ih , zz = v il. all their inputs = v ih or v il , l out = 0 ) l sbzz l sbss - - tbd ma ma 1 1 input leakage current (v in = v ss or v dd ) l li - 1.0 m a output leakage current (v out = v ss or v dd , dq in high = z) l lo - 1.0 m a output high level voltage(l oh = -6ma @ v ddq /2 +0.3 ) v oh v ddq -.4 v ddq v 2 output low level voltage(l ol = +6ma @ v ddq /2 -0.3 ) v ol v ss v ss +.4 v 2 1. l out = chip output current. 2.minimum impedance output driver.
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 7 amic technology, inc. capacitance (t j = 0 to +110 c, v dd = 3.3v 5%, f = 1mhz ) parameter symbol test condition max. units input capacitance c in v in = 0v 3 pf data i/o capacitance (dq0-dq35) c out v out = 0v 4 pf ac input characteristics item symbol min. max. notes ac input logic high v in (ac) tbd 3 ac input logic low v il (ac) tbd 3 clock input differential voltage v dif (ac) tbd 2 v ref peak to peak ac voltage v ref (ac) 5% v ref (dc) 1 1.the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2.performance is a function on v ih and v il levels to clock inputs. 3.see ac input definition figure on page 7. ac input definition v ih (ac) v ref v il (ac)
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 8 amic technology, inc. programmable impedance output driver dc electrical characteristics (t j = 0 to +110 c, v dd = 3.3v 5% ) parameter symbol min. max. units notes output high level voltage v oh v ddq /2 v ddq v 1 output low level voltage v ol v ss v ddq /2 v 2 1.l oh = (v ddq /2)/(rq/5) 7.5% @ v oh = v ddq /2 for :150 w rq 350 w 2.l ol = (v ddq /2)/(rq/5) 7.5% @ v ol = v ddq /2 for :150 w rq 350 w a c test conditions (t j = 0 to +110 c, v dd = 3.3v 5%, v ddq = 1.5v ) parameter symbol conditions units notes output high level voltage v ih 1.25 v output low level voltage v il 0.25 v input reference voltage v ref 0.75 v differential clocks voltage v dif-clk 0.75 v input rise time t r 0.5 ns input fall time t f 0.5 ns i/o signals reference level 0.75 v clocks reference level differential cross point v output load conditions 1 1.see ac test loading figure on page 8. a c test loading 50 w 250 w 50 w v ddo /2 device under test 0.75v v ref zq
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 9 amic technology, inc. ac characteristics (t j = 0 to +110 c, v dd = 3.3v 5% ) parameter symbol -5 -6 -7 units notes min. max. min. max. min. max. cycle time t khkh 5 - 6.0 - 7.0 - ns clock high pulse width t khkl 1.5 - 1.5 - 1.5 - ns clock low pulse width t klkh 1.5 - 1.5 - 1.5 - ns clock to output valid t khqv - 2.5 3.0 - 3.5 ns 1 address setup time t avkh 0.5 - 0.5 - 0.5 - ns 4 address hold time t khax 1.0 - 1.0 - 1.0 - ns 4 sync select setup time t svkh 0.5 - 0.5 - 0.5 - ns 4 sync select hold time t khsx 1.0 - 1.0 - 1.0 - ns 4 write enables setup time t wvkh 0.5 - 0.5 - 0.5 - ns 4 write enables hold time t khwx 1.0 - 1.0 - 1.0 - ns 4 data in setup time t dvkh 0.5 - 0.5 - 0.5 - ns 4 data in hold time t khdx 1.0 - 1.0 - 1.0 - ns 4 data out hold time t khqx 0.5 - 0.5 - 0.5 - ns 1 clock high to output high-z t khqz - 2.5 - 3.0 - 3.5 ns 1, 2 clock high to output active t xhqx4 1.0 - 1.0 - 1.0 - ns 1, 2 output enable to high-z t ghqz - 2.5 3.0 - 3.5 ns 1, 2 output enable to low-z t glqx 0.5 - 0.5 - 0.5 - ns 1, 2 output enable to output valid t glqv - 2.5 - 3.0 - 3.5 ns 1 output enable setup time t ghkh 0.5 - 0.5 - 0.5 - ns 1, 3 output enable hold time t khgx 1.5 - 1.5 - 1.5 - ns 1, 3 sleep mode recovery time t zzr 5 - 6 - 7 - ns sleep mode enable time t zze - 5 - 6 - 7 ns 1.see ac test loading figure on page 8. 2.transitions are measured 200mv from steady state voltage. 3.output driver impedance update specifications for g induced updates. write and deselect cycles will also induce output driver updates during high-z. 4.inuse conditions v ih , v il , trise, tfall of inputs must be withim 20% of v ih , v il , trise, tfall of clock.
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 10 amic technology, inc. timing diagram (read and deselect cycles) t khax t klkh t khkl t khkh ck sa ss sw g dq t avkh a1 a2 a3 a4 t khsx t svkh t wvkh t ghqz q1 q2 q3 a3 q4 t glqv t glqx t khqv t khqx t khqz t khqx4 t khqv t khwx
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 11 amic technology, inc. timing diagram (read write cycles) t khax t klkh t khkl t khkh ck sa ss sw g dq t avkh a1 a2 a3 a4 t khsx t svkh q3 a2 t khqv t khqz t khqx4 t khdx t khwx t xhwx t wvkh sbw t wvkh t wvkh t khwx t wvkh t xhwx t ghqz q2 t dvkh t khdx t khqv t dvkh d4 q1 d2 notes: 1.d2 is the input data write in memory location a2. 2.q2 is output data read from the write buffer, as a result of address a2 being a match from the last write cycle address .
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 12 amic technology, inc. timing diagram (sleep mode) t zze t khkh t zzr ck zz dq
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 13 amic technology, inc. ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions intended to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee std. 1149.1, the sram contains a tap controller, instruction register, boundary scan register, bypass register and id register. the tap controller has a standard 16-state machine that resets internally upon power-up, therefore, trst signal is not required. signal list l tck : test clock l tms : test mode select l tdi : test data in l tdo : test data out caution: tck, tms, tdi must be tied down, even if jtag is not used. jtag recommended dc operating conditions (t j = 0 to 110 c) parameter symbol min. typ. max. units notes jtag input high voltage v ih1 2.2 - v dd + 0.3 v 1 jtag input low voltage v il1 -03 - 0.8 v 1 jtag output high level v oh1 2.4 - - v 1,2 jtag output low level v ol1 - - 0.4 v 1,3 1. all jtag inputs/outputs are lvttl compatible only. 2. i oh1 = -8ma at 2.4v. 3. i ol1 = +8ma at 0.4v. jtag recommended dc operating conditions (t j = 0 to 110 c) parameter symbol conditions units notes input pulse high level v ih1 3.0 v input pulse low level v il1 0.0 v input rise time t r1 2.0 ns input fall time t f1 2.0 ns input and output timing reference level 1.5 v 1 1. see ac test loading on page 8.
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 14 amic technology, inc. jtag ac characteristics (t j = 0 to 110 c, v dd = 3.3v 5%) parameter symbol min. max. units notes tck cycle time t thth 20 - ns tck high pulse width t thtl 7 - ns tck low pulse width t tlth 7 - ns tms setup t mvth 4 - ns tms hold t thmx 4 - ns tdi setup t dvth 4 - ns tdi hold t thdx 4 - ns tck low to valid data t tlov - 7 ns 1 1. see ac test loading on page 8. jtag timing diagram t thtl t tlth t thth t thmx t mvth t thdx t dvth t tlov tck tms tdi tdo
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 15 amic technology, inc. scan register definition register name bit size x18 bit size x 36 instruction 3 3 bypass 1 1 id 32 32 boundary scan* 51 70 * the boundary scan chain consists of the following bits : 36 or 18 bits for data inputs depending on x 18 or x 36 configuration 15 bits for sa0 - sa14 for x 36, 16 bits for sa0 - sa15 for x 18 4 bits for sbwa - sbwd in x 36, 2 bits for sbwa and sbwb x 18 9 bits for ck, ck , zq, ss , g , sw , zz, m1 and m2 6 bits for place holders * ck and ck clocks connect to a differential receiver that generates a single-ended clock signal. this signal and its inverted value are used for boundary scan sampling. id register definition field bit number and description part revision number (31 : 28) device density and configuration (27 : 18) vender definition (17 : 12) manufacture jedec code (11 : 1) start bit (0) 256k x 18 0001 100 000 0110 000001 000 101 111 11 1 128k x 36 0001 011 100 1101 100001 000 101 111 11 1 instruction set code instruction notes 000 sample-z 1 001 idcode 1 010 sample-z 1 011 private 3 100 sample 4 101 private 3 110 private 3 111 bypass 3 1. places dqs in high-z in order to sample all input data regardless of the other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to vss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift dr state. 4. sample instruction does not place dqs in high-z list of ieee 1149.1 standard violations : 7.2.1.b,e 7.7.1.a-f 10.1.1.b,e 10.7.1.a-d 6.1.1.d
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 16 amic technology, inc. boundary scan order (x 36) exit order signal bump # exit order signal bump # exit order signal bump # 1 m2 5r 25 dq13 6f 49 dq26 2h 2 sa1 4p 26 dq11 7e 50 dq25 1h 3 sa2 4t 27 dq12 6e 51 sbwc 3g 4 sa12 6r 28 dq9 7d 52 zq 4d 5 sa13 5t 29 dq10 6d 53 ss 4e 6 zz 7t 30 sa14 6a 54 nc 4g 7 dq1 6p 31 sa15 6c 55 nc 4h 8 dq0 7p 32 sa10 5c 56 sw 4m 9 dq3 6n 33 sa16 5a 57 sbwd 3l 10 dq2 7n 34 nc 6b 58 dq34 1k 11 dq4 6m 35 sa11 5b 59 dq35 2k 12 dq6 6l 36 sa8 3b 60 dq32 1l 13 dq5 7l 37 nc 2b 61 dq33 2l 14 dq8 6k 38 sa7 3a 62 dq31 2m 15 dq7 7k 39 sa9 3c 63 dq29 1n 16 sbwa 5l 40 sa6 2c 64 dq30 2n 17 ck 4l 41 sa5 2a 65 dq27 1p 18 ck 4k 42 dq19 2d 66 dq28 2p 19 g 4f 43 dq18 1d 67 sa3 3t 20 sbwb 5g 44 dq21 2e 68 sa4 2r 21 dq16 7h 45 dq20 1e 69 sa0 4n 22 dq17 6h 46 dq22 2f 70 m1 3r 23 dq14 7g 47 dq24 2g 24 dq15 6g 48 dq23 1g
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 17 amic technology, inc. boundary scan order (x 18) exit order signal bump # exit order signal bump # 1 m2 5r 27 nc 2b 2 sa12 6t 28 sa7 3a 3 sa1 4p 29 sa9 3c 4 sa13 6r 30 sa6 2c 5 sa17 5t 31 sa5 2a 6 zz 7t 32 dq9 1d 7 dq0 7p 33 dq12 2e 8 dq3 6n 43 dq15 2g 9 dq6 6l 35 dq16 1h 10 dq7 7k 36 sbwb 3g 11 sbwa 5l 37 zq 4d 12 ck 4l 38 ss 4e 13 ck 4k 39 nc 4g 14 g 4f 40 nc 4h 15 dq8 6h 41 sw 4m 16 dq5 7g 42 dq17 2k 17 dq4 6f 43 dq14 1l 18 dq2 7e 44 dq13 2m 19 dq1 6d 45 dq11 1n 20 sa14 6a 46 dq10 2p 21 sa15 6c 47 sa3 3t 22 sa10 5c 48 sa4 2r 23 sa16 5a 49 sa0 4n 24 nc 6b 50 sa2 2t 25 sa11 5b 51 m1 3r 26 sa8 3b
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 18 amic technology, inc. tap controller state machine test logic reset run test idle select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 0 select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir 1 0 1 0 1 1 0 0 0 0 0 1 1 1 1 1
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 19 amic technology, inc. ordering information part number organization speed package a65h83181p-5 256k x 18 2.5ns access / 5 ns cycle 7 x 17 pbga a65h83181p-6 256k x 18 3.0ns access / 6 ns cycle 7 x 17 pbga a65h83181p-7 256k x 18 3.5ns access / 7 ns cycle 7 x 17 pbga a65h73361p-5 128k x 36 2.5ns access / 5 ns cycle 7 x 17 pbga a65h73361p-6 128k x 36 3.0ns access / 6 ns cycle 7 x 17 pbga A65H73361P-7 128k x 36 3.5ns access / 7 ns cycle 7 x 17 pbga
a65h73361/a65h83181 series preliminary (february, 1999, version 2.0) 20 amic technology, inc. package information 14.00 0.10 22.00 0.10 20.00 0.05 pin #1 1.96 (min) 2.36 (max) 30 2 1.00 0.05 0.60 0.10 20.32 0.10 -a- -b- 7.62 0.10 7 6 5 4 3 2 1 0.30 s c a s b s 0.10 s c 12.00 0.05 1.56 0.56 1.270 typ. -c- 0.15 c d seating plane note: 1. all dimensions are millimeters. 2. details of molded plastic body may vary from that shown. 1.27 typ . 119x f 0.80 0.1 a b c d e f g h j k l m n p r t u

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